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DAC
2005
ACM
15 years 10 months ago
2005
ACM
As the d esig n-m anu factu ring interface becom es increasing ly com plicated with IC technolog y scaling , the correspond ing process variability poses g reat challeng es for na...
JCP
2008
14 years 9 months ago
2008
Sleep transistors in industrial power-gating designs are custom designed with an optimal size. Consequently, sleep transistor P/G network optimization becomes a problem of finding ...
ETFA
2005
IEEE
15 years 3 months ago
2005
IEEE
Global competition has given rise to Logistic and Production Systems (LPSs), that are distributed manufacturing systems integrating international logistics and information technol...
ICCAD
2007
IEEE
2007
IEEE
Optimal polynomial-time interprocedural register allocation for high-level synthesis and ASIP design
15 years 6 months ago
—Register allocation, in high-level synthesis and ASIP design, is the process of determining the number of registers to include in the resulting circuit or processor. The goal is...
DT
2000
14 years 9 months ago
2000
The design of complex embedded systems involves the simultaneous optimization of several often competing objectives. Instead of a single optimal design, there is rather a set of a...