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PPOPP
2006
ACM
15 years 8 months ago
McRT-STM: a high performance software transactional memory system for a multi-core runtime
Applications need to become more concurrent to take advantage of the increased computational power provided by chip level multiprocessing. Programmers have traditionally managed t...
Bratin Saha, Ali-Reza Adl-Tabatabai, Richard L. Hu...
PVM
2009
Springer
15 years 8 months ago
Hierarchical Collectives in MPICH2
Abstract. Most parallel systems on which MPI is used are now hierarchical: some processors are much closer to others in terms of interconnect performance. One of the most common su...
Hao Zhu, David Goodell, William Gropp, Rajeev Thak...
CDES
2010
184views Hardware» more  CDES 2010»
15 years 8 days ago
Delay-Insensitive Cell Matrix
This paper describes the design of a delay-insensitive (DI) Cell Matrix. This architecture allows for massively parallel, self-determined operation and can be used to implement reg...
Scott Smith, David Roclin, Jia Di
HCW
1998
IEEE
15 years 6 months ago
NetSolve: A Network-Enabled Solver; Examples and Users
The NetSolve project, underway at the University of Tennessee and at the Oak Ridge National Laboratory, allows users to access computational resources distributed across the netwo...
Henri Casanova, Jack Dongarra
INFOCOM
2006
IEEE
15 years 8 months ago
Holographic and 3D Teleconferencing and Visualization: Implications for Terabit Networked Applications
— We discuss the evolution of teleconferencing and networked visualization applications to support 3-dimensional display technologies. The implications of a continuation of Moore...
Ladan Gharai, Colin Perkins