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» Designing a DHT for Low Latency and High Throughput
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ANCS
2010
ACM
14 years 7 months ago
DOS: a scalable optical switch for datacenters
This paper discusses the architecture and performance studies of Datacenter Optical Switch (DOS) designed for scalable and highthroughput interconnections within a data center. DO...
Xiaohui Ye, Yawei Yin, S. J. Ben Yoo, Paul Vincent...
ISLPED
2005
ACM
103views Hardware» more  ISLPED 2005»
15 years 3 months ago
A technique for low energy mapping and routing in network-on-chip architectures
Network-on-chip (NoC) has been proposed as a solution for the global communication challenges of System-on-chip (SoC) design in the nanoscale technologies. NoC design with mesh ba...
Krishnan Srinivasan, Karam S. Chatha
DAC
2009
ACM
15 years 2 months ago
A computing origami: folding streams in FPGAs
Stream processing represents an important class of applications that spans telecommunications, multimedia and the Internet. The implementation of streaming programs in FPGAs has a...
Andrei Hagiescu, Weng-Fai Wong, David F. Bacon, Ro...
TWC
2008
92views more  TWC 2008»
14 years 9 months ago
Multi-layer broadcasting hybrid-ARQ strategies for block fading channels
Conventional hybrid automatic retransmission request (HARQ) is usually used to maximize throughput. However, high throughput is achieved at the expense of high latency. We study a...
Avi Steiner, Shlomo Shamai
75
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal