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» Designing a DHT for Low Latency and High Throughput
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HPCA
1996
IEEE
15 years 1 months ago
Co-Scheduling Hardware and Software Pipelines
Exploiting instruction-level parallelism (ILP) is extremely important for achieving high performance in application specific instruction set processors (ASIPs) and embedded process...
Ramaswamy Govindarajan, Erik R. Altman, Guang R. G...
62
Voted
IPPS
2007
IEEE
15 years 4 months ago
File Creation Strategies in a Distributed Metadata File System
As computing breaches petascale limits both in processor performance and storage capacity, the only way that current and future gains in performance can be achieved is by increasi...
Ananth Devulapalli, Pete Wyckoff
ISCA
1997
IEEE
108views Hardware» more  ISCA 1997»
15 years 1 months ago
The SGI Origin: A ccNUMA Highly Scalable Server
The SGI Origin 2000 is a cache-coherent non-uniform memory access (ccNUMA) multiprocessor designed and manufactured by Silicon Graphics, Inc. The Origin system was designed from t...
James Laudon, Daniel Lenoski
HPCA
2011
IEEE
14 years 1 months ago
A new server I/O architecture for high speed networks
Traditional architectural designs are normally focused on CPUs and have been often decoupled from I/O considerations. They are inefficient for high-speed network processing with a...
Guangdeng Liao, Xia Znu, Laxmi N. Bhuyan
60
Voted
ISLPED
2007
ACM
110views Hardware» more  ISLPED 2007»
14 years 11 months ago
A 0.4-V UWB baseband processor
A 0.4-V UWB digital baseband processor has been fabricated in a standard-VT 90-nm CMOS technology. The baseband processor operates at an ultra-low supply voltage to reduce energy ...
Vivienne Sze, Anantha P. Chandrakasan