377 search results - page 57 / 76 » Designing a DHT for Low Latency and High Throughput |
96
Voted
ISCA
2012
IEEE
13 years 2 days ago
2012
IEEE
Modern DRAMs have multiple banks to serve multiple memory requests in parallel. However, when two requests go to the same bank, they have to be served serially, exacerbating the h...
ICCCN
2008
IEEE
15 years 4 months ago
2008
IEEE
—Parallel firewalls offer a scalable low latency design for inspecting packets at high speeds. Typically consisting of an array of m firewalls, these systems filter arriving p...
FPL
2008
Springer
14 years 11 months ago
2008
Springer
An example of an FPGA based application for a high-energy physics experiment is presented which features all facets of modern FPGA design. The special requirements here are high b...
106
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CASES
2007
ACM
2007
ACM
INTACTE: an interconnect area, delay, and energy estimation tool for microarchitectural explorations
15 years 1 months ago
Prior work on modeling interconnects has focused on optimizing the wire and repeater design for trading off energy and delay, and is largely based on low level circuit parameters....
ICCD
2006
IEEE
15 years 6 months ago
2006
IEEE
Abstract— Microcode enables programmability of (micro) architectural structures to enhance functionality and to apply patches to an existing design. As more features get added to...