377 search results - page 5 / 76 » Designing a DHT for Low Latency and High Throughput |
NOCS
2010
IEEE
14 years 7 months ago
2010
IEEE
Router microarchitecture plays a central role in the performance of an on-chip network (NoC). Buffers are needed in routers to house incoming flits which cannot be immediately forw...
ICCCN
2007
IEEE
15 years 3 months ago
2007
IEEE
—Multimedia requirements of the 1990’s drove wired and optical network architects to reconsider the inefficiencies of packet switching and consider long proven methods such as...
HIPEAC
2009
Springer
15 years 4 months ago
2009
Springer
In this article, we present a parallel implementation of a 1024 point Fast Fourier Transform (FFT) operating with a subthreshold supply voltage, which is below the voltage that tur...
IPPS
2007
IEEE
15 years 3 months ago
2007
IEEE
High-radix switches are desirable building blocks for large computer interconnection networks, because they are more suitable to convert chip I/O bandwidth into low latency and lo...
ANCS
2007
ACM
15 years 1 months ago
2007
ACM
Scheduling in large switches is challenging. Arbiters must operate at high rates to keep up with the high switching rates demanded by multi-gigabit-per-second link rates and short...