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FPGA
2006
ACM
98views FPGA» more  FPGA 2006»
15 years 7 months ago
A reconfigurable hardware based embedded scheduler for buffered crossbar switches
In this paper, we propose a new internally buffered crossbar (IBC) switching architecture where the input and output distributed schedulers are embedded inside the crossbar fabric...
Lotfi Mhamdi, Christopher Kachris, Stamatis Vassil...
DATE
2008
IEEE
109views Hardware» more  DATE 2008»
15 years 10 months ago
Layout-Aware, IR-Drop Tolerant Transition Fault Pattern Generation
— Market and customer demands have continued to push the limits of CMOS performance. At-speed test has become a common method to ensure these high performance chips are being shi...
Jeremy Lee, Sumit Narayan, Mike Kapralos, Mohammad...
IPPS
1996
IEEE
15 years 8 months ago
Implementation of a SliM Array Processor
This paper presents the design and implementation of a Sliding Memory Plane (SliM) Array Processor, a mesh-connected SIMD architecture. To build the array processor, we developed ...
Hyun M. Chang, Myung Hoon Sunwoo, Tai-Hoon Cho
SIGECOM
2011
ACM
259views ECommerce» more  SIGECOM 2011»
14 years 6 months ago
Designing adaptive trading agents
ended abstract summarizes the research presented in Dr. Pardoe’s recently-completed Ph.D. thesis [Pardoe 2011]. The thesis considers how adaptive trading agents can take advantag...
David Pardoe, Peter Stone
VLSID
2006
IEEE
150views VLSI» more  VLSID 2006»
16 years 4 months ago
A Comprehensive SoC Design Methodology for Nanometer Design Challenges
SoC design methodologies are under constant revision due to adoption of fast shrinking process technologies at nanometer levels. Nanometer process geometries exhibit new complex d...
R. Raghavendra Kumar, Ricky Bedi, Ramadas Rajagopa...