Sciweavers

4394 search results - page 251 / 879
» Designing agent chips
Sort
View
ARCS
2005
Springer
15 years 11 months ago
Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems
Abstract. The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and ...
Vincent Kotzsch, Jörg Schneider, Günther...
181
Voted
DAC
1999
ACM
15 years 10 months ago
Reducing Cross-Coupling Among Interconnect Wires in Deep-Submicron Datapath Design
As the CMOS technology enters the deep submicron design era, the lateral inter-wire coupling capacitance becomes the dominant part of load capacitance and makes RC delay on the bu...
Joon-Seo Yim, Chong-Min Kyung
FPL
1997
Springer
78views Hardware» more  FPL 1997»
15 years 10 months ago
Run-time compaction of FPGA designs
Controllers for dynamically recon gurable FPGAs that are capable of supporting multiple independent tasks simultaneously need to be able to place designs at run{time when the seque...
Oliver Diessel, Hossam A. ElGindy
ATS
2001
IEEE
126views Hardware» more  ATS 2001»
15 years 10 months ago
Design of an Optimal Test Access Architecture Using a Genetic Algorithm
Test access is a major problem for core-based systemon-chip (SOC) designs. Since cores in an SOC are not directly accessible via chip inputs and outputs, special access mechanisms...
Zahra Sadat Ebadi, André Ivanov
ISLPED
2007
ACM
92views Hardware» more  ISLPED 2007»
15 years 7 months ago
Variable-latency adder (VL-adder): new arithmetic circuit design practice to overcome NBTI
Negative bias temperature instability (NBTI) has become a dominant reliability concern for nanoscale PMOS transistors. In this paper, we propose variable-latency adder (VL-adder) ...
Yiran Chen, Hai Li, Jing Li, Cheng-Kok Koh