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ISQED
2008
IEEE
66views Hardware» more  ISQED 2008»
15 years 6 months ago
An Implementation of Performance-Driven Block and I/O Placement for Chip-Package Codesign
– As silicon technology scales, we can integrate more and more circuits on a single chip, which means more I/Os are needed in modern designs. The flip-chip technology which was ...
Ming-Fang Lai, Hung-Ming Chen
CF
2007
ACM
15 years 3 months ago
Massively parallel processing on a chip
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
Philippe Marquet, Simon Duquennoy, Sébastie...
DATE
2004
IEEE
129views Hardware» more  DATE 2004»
15 years 3 months ago
Cost-Performance Trade-Offs in Networks on Chip: A Simulation-Based Approach
A challenge facing designers of systems on chip (SoC) containing networks on chip (NoC) is to find NoC instances that balance the cost (e.g. area) and performance (e.g. latency an...
Santiago González Pestana, Edwin Rijpkema, ...
IWSOC
2005
IEEE
121views Hardware» more  IWSOC 2005»
15 years 5 months ago
Open HW, Open Design SW, and the VC Ecosystem Dilemma
The open model for solutions development is quickly extending from software to other technology areas, such as hardware and services. Specifically, just as open source has spawned...
Juan Antonio Carballo
MATA
2001
Springer
158views Communications» more  MATA 2001»
15 years 4 months ago
Network Processing of Mobile Agents, by Mobile Agents, for Mobile Agents
This paper presents a framework for building network protocols for migrating mobile agents over a network. The framework allows network protocols for agent migration to be naturall...
Ichiro Satoh