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RTCSA
2008
IEEE
15 years 6 months ago
Concepts of Switching in the Time-Triggered Network-on-Chip
This paper presents the concepts of switching in the Time-Triggered Network-on-Chip (TTNoC), which is the communication subsystem of the Time-Triggered Systemon-Chip (TTSoC) archi...
Christian Paukovits, Hermann Kopetz
DAC
1999
ACM
15 years 4 months ago
On-Chip Inductance Issues in Multiconductor Systems
As the family of Alpha microprocessors continues to scale into more advanced technologies with very high frequency edge rates and multiple layers of interconnect, the issue of cha...
Shannon V. Morton
ITC
1996
IEEE
96views Hardware» more  ITC 1996»
15 years 4 months ago
Analysis and Detection of Timing Failures in an Experimental Test Chip
A 25k gate Test Chip was designed and manufactured to evaluate different test methods for scan-designed circuits. The design of the chip, the experiment, and preliminary experimen...
Piero Franco, Siyad C. Ma, Jonathan Chang, Yi-Chin...
ICCD
2008
IEEE
159views Hardware» more  ICCD 2008»
15 years 8 months ago
Optimizing data sharing and address translation for the Cell BE Heterogeneous Chip Multiprocessor
— Heterogeneous Chip Multiprocessors (HMPs), such as the Cell Broadband Engine, offer a new design optimization opportunity by allowing designers to provide accelerators for appl...
Michael Gschwind
IEEEPACT
2009
IEEE
15 years 6 months ago
Characterizing the TLB Behavior of Emerging Parallel Workloads on Chip Multiprocessors
Translation Lookaside Buffers (TLBs) are a staple in modern computer systems and have a significant impact on overall system performance. Numerous prior studies have addressed TL...
Abhishek Bhattacharjee, Margaret Martonosi