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DAC
1996
ACM
15 years 8 months ago
Sizing of Clock Distribution Networks for High Performance CPU Chips
: In a high performance microprocessor such as Digital's 300MHz Alpha 21164, the distribution of a high quality clock signal to all regions of the device is achieved using a c...
Madhav P. Desai, Radenko Cvijetic, James Jensen
HIPEAC
2009
Springer
15 years 7 months ago
ACM: An Efficient Approach for Managing Shared Caches in Chip Multiprocessors
This paper proposes and studies a hardware-based adaptive controlled migration strategy for managing distributed L2 caches in chip multiprocessors. Building on an area-efficient sh...
Mohammad Hammoud, Sangyeun Cho, Rami G. Melhem
ASYNC
2005
IEEE
79views Hardware» more  ASYNC 2005»
15 years 5 months ago
A Scheduling Discipline for Latency and Bandwidth Guarantees in Asynchronous Network-on-Chip
Guaranteed services (GS) are important in that they provide predictability in the complex dynamics of shared communication structures. This paper discusses the implementation of G...
Tobias Bjerregaard, Jens Sparsø
CAL
2007
15 years 3 months ago
Nahalal: Cache Organization for Chip Multiprocessors
— This paper addresses cache organization in Chip Multiprocessors (CMPs). We show that in CMP systems it is valuable to distinguish between shared data, which is accessed by mult...
Zvika Guz, Idit Keidar, Avinoam Kolodny, Uri C. We...
ICCAD
2009
IEEE
113views Hardware» more  ICCAD 2009»
15 years 1 months ago
A performance analytical model for Network-on-Chip with constant service time routers
Performance models for Network-on-Chip (NoC) are essential for design, optimization and Quality of Service (QoS) assurance. Classical queueing theory has been often used to provid...
Nikita Nikitin, Jordi Cortadella