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IPPS
2005
IEEE
15 years 8 months ago
Designing Scalable FPGA-Based Reduction Circuits Using Pipelined Floating-Point Cores
The use of pipelined floating-point arithmetic cores to create high-performance FPGA-based computational kernels has introduced a new class of problems that do not exist when usi...
Ling Zhuo, Gerald R. Morris, Viktor K. Prasanna
ICC
2008
IEEE
115views Communications» more  ICC 2008»
15 years 9 months ago
Joint Power Scheduling and Estimator Design for Sensor Networks Across Parallel Channels
—This paper addresses the joint estimator and power optimization problem for a sensor network whose mission is to estimate an unknown parameter. We assume a two-hop network where...
Lauren M. Huie, Xiang He, Aylin Yener
CONEXT
2009
ACM
15 years 4 months ago
Online optimization of 802.11 mesh networks
802.11 wireless mesh networks are ubiquitous, but suffer from severe performance degradations due to poor synergy between the 802.11 CSMA MAC protocol and higher layers. Several s...
Theodoros Salonidis, Georgios Sotiropoulos, Roch G...
CDC
2009
IEEE
160views Control Systems» more  CDC 2009»
15 years 7 months ago
Control of impulsive renewal systems: Application to direct design in networked control
— We consider the control of impulsive systems with jumps triggered by a renewal process, that is, the intervals between jumps are independent and identically distributed. The co...
Duarte Antunes, João Pedro Hespanha, Carlos...
CCS
2004
ACM
15 years 8 months ago
IP covert timing channels: design and detection
A network covert channel is a mechanism that can be used to leak information across a network in violation of a security policy and in a manner that can be difficult to detect. In...
Serdar Cabuk, Carla E. Brodley, Clay Shields