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DATE
2005
IEEE
108views Hardware» more  DATE 2005»
15 years 10 months ago
A Technology-Aware and Energy-Oriented Topology Exploration for On-Chip Networks
As packet-switching interconnection networks replace buses and dedicated wires to become the standard on-chip interconnection fabric, reducing their power consumption has been ide...
Hangsheng Wang, Li-Shiuan Peh, Sharad Malik
DATE
2007
IEEE
173views Hardware» more  DATE 2007»
15 years 11 months ago
Analytical router modeling for networks-on-chip performance analysis
Networks-on-Chip (NoCs) have recently emerged as a scalable alternative to classical bus and point-to-point architectures. To date, performance evaluation of NoC designs is largel...
Ümit Y. Ogras, Radu Marculescu
SIGMOD
2008
ACM
102views Database» more  SIGMOD 2008»
16 years 5 months ago
ProSem: scalable wide-area publish/subscribe
We demonstrate ProSem, a scalable wide-area publish/subscribe system that supports complex, stateful subscriptions as well as simple ones. One unique feature of ProSem is its cost...
Badrish Chandramouli, Jun Yang 0001, Pankaj K. Aga...
BMCBI
2008
123views more  BMCBI 2008»
15 years 4 months ago
Validation of protein models by a neural network approach
Background: The development and improvement of reliable computational methods designed to evaluate the quality of protein models is relevant in the context of protein structure re...
Paolo Mereghetti, Maria Luisa Ganadu, Elena Papale...
ISPA
2004
Springer
15 years 10 months ago
Cayley DHTs - A Group-Theoretic Framework for Analyzing DHTs Based on Cayley Graphs
Static DHT topologies influence important features of such DHTs such as scalability, communication load balancing, routing efficiency and fault tolerance. Nevertheless, it is co...
Changtao Qu, Wolfgang Nejdl, Matthias Kriesell