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TC
2011
14 years 11 months ago
Maximizing Spare Utilization by Virtually Reorganizing Faulty Cache Lines
—Aggressive technology scaling to 45nm and below introduces serious reliability challenges to the design of microprocessors. Since a large fraction of chip area is devoted to on-...
Amin Ansari, Shantanu Gupta, Shuguang Feng, Scott ...
FPL
2009
Springer
161views Hardware» more  FPL 2009»
15 years 9 months ago
A multi-FPGA architecture for stochastic Restricted Boltzmann Machines
Although there are many neural network FPGA architectures, there is no framework for designing large, high-performance neural networks suitable for the real world. In this paper, ...
Daniel L. Ly, Paul Chow
GECCO
2007
Springer
178views Optimization» more  GECCO 2007»
15 years 10 months ago
Coevolution of intelligent agents using cartesian genetic programming
A coevolutionary competitive learning environment for two antagonistic agents is presented. The agents are controlled by a new kind of computational network based on a compartment...
Gul Muhammad Khan, Julian Francis Miller, David M....
GECCO
2007
Springer
212views Optimization» more  GECCO 2007»
15 years 10 months ago
A developmental model of neural computation using cartesian genetic programming
The brain has long been seen as a powerful analogy from which novel computational techniques could be devised. However, most artificial neural network approaches have ignored the...
Gul Muhammad Khan, Julian F. Miller, David M. Hall...
DATE
2000
IEEE
124views Hardware» more  DATE 2000»
15 years 8 months ago
On the Generation of Multiplexer Circuits for Pass Transistor Logic
Pass Transistor Logic has attracted more and more interest during last years, since it has proved to be an attractive alternative to static CMOS designs with respect to area, perf...
Christoph Scholl, Bernd Becker