Sciweavers

453 search results - page 14 / 91
» Designing hardware with dynamic memory abstraction
Sort
View
68
Voted
IEEEHPCS
2010
14 years 8 months ago
Retargeting PLAPACK to clusters with hardware accelerators
Hardware accelerators are becoming a highly appealing approach to boost the raw performance as well as the price-performance and power-performance ratios of current clusters. In t...
Manuel Fogue, Francisco D. Igual, Enrique S. Quint...
ASAP
2010
IEEE
193views Hardware» more  ASAP 2010»
14 years 11 months ago
Automatic generation of polynomial-based hardware architectures for function evaluation
Abstract--Polynomial approximation is a very general technique for the evaluation of a wide class of numerical functions of one variable. This article details an architecture gener...
Florent de Dinechin, Mioara Joldes, Bogdan Pasca
114
Voted
ISCA
2012
IEEE
232views Hardware» more  ISCA 2012»
13 years 1 days ago
RADISH: Always-on sound and complete race detection in software and hardware
Data-race freedom is a valuable safety property for multithreaded programs that helps with catching bugs, simplifying memory consistency model semantics, and verifying and enforci...
Joseph Devietti, Benjamin P. Wood, Karin Strauss, ...
COMPUTER
1998
94views more  COMPUTER 1998»
14 years 9 months ago
Multiprocessors Should Support Simple Memory-Consistency Models
provide tools or abstractions that allow developers to program in parallel. But what hardware do we need to support shared memory threads? The hardware should provide a well-defin...
Mark D. Hill
WWIC
2004
Springer
133views Communications» more  WWIC 2004»
15 years 3 months ago
Design of Energy Efficient Wireless Networks Using Dynamic Data Type Refinement Methodology
Abstract. This paper presents a new perspective to the design of wireless networks using the proposed dynamic data type refinement methodology. In the forthcoming years, new portab...
Stylianos Mamagkakis, Alexandros Mpartzas, Georgio...