453 search results - page 39 / 91 » Designing hardware with dynamic memory abstraction |
108
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ISCA
2012
IEEE
13 years 4 days ago
2012
IEEE
Hybrid processors are HW/SW co-designed processors that leverage blocked-execution, the execution of regions of instructions as atomic blocks, to facilitate aggressive speculative...
ICECCS
1996
IEEE
15 years 1 months ago
1996
IEEE
A dynamically reconfigurable real-time software (DRRTS) paradigm can be used effectively in the design of embedded systems to provide many major advantages over conventional softw...
ISCA
2002
IEEE
15 years 2 months ago
2002
IEEE
An increasingly large portion of scheduler latency is derived from the monolithic content addressable memory (CAM) arrays accessed during instruction wakeup. The performance of th...
121
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WMPI
2004
ACM
15 years 3 months ago
2004
ACM
Abstract. The large and growing impact of memory hierarchies on overall system performance compels designers to investigate innovative techniques to improve memory-system efficienc...
112
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IEEEPACT
2005
IEEE
15 years 3 months ago
2005
IEEE
Feedback-directed Optimization has become an increasingly important tool in designing and building optimizing compilers as itprovides a means to analyze complexprogram behavior th...