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» Designing hardware with dynamic memory abstraction
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FPL
2008
Springer
138views Hardware» more  FPL 2008»
14 years 11 months ago
An efficient run-time router for connecting modules in FPGAS
It is often desirable to change the logic and/or the connections within an FPGA design on-the-fly without the benefit of a workstation or vendor CAD software. This paper presents ...
Jorge Surís, Cameron Patterson, Peter Athan...
ASPLOS
2012
ACM
13 years 5 months ago
A case for unlimited watchpoints
Numerous tools have been proposed to help developers fix software errors and inefficiencies. Widely-used techniques such as memory checking suffer from overheads that limit thei...
Joseph L. Greathouse, Hongyi Xin, Yixin Luo, Todd ...
LCPC
2009
Springer
15 years 2 months ago
A Balanced Approach to Application Performance Tuning
Abstract. Current hardware trends place increasing pressure on programmers and tools to optimize scientific code. Numerous tools and techniques exist, but no single tool is a pana...
Souad Koliai, Stéphane Zuckerman, Emmanuel ...
ARCS
2005
Springer
15 years 3 months ago
Reusable Design of Inter-chip Communication Interfaces for Next Generation of Adaptive Computing Systems
Abstract. The SoC (System-on-Chip) technology is used in small and flexible consumer electronic devices. SoCs include one or more microcontroller, memory, programmable logic, and ...
Vincent Kotzsch, Jörg Schneider, Günther...
ISCA
2009
IEEE
318views Hardware» more  ISCA 2009»
15 years 4 months ago
Thread criticality predictors for dynamic performance, power, and resource management in chip multiprocessors
With the shift towards chip multiprocessors (CMPs), exploiting and managing parallelism has become a central problem in computer systems. Many issues of parallelism management boi...
Abhishek Bhattacharjee, Margaret Martonosi