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» Designing hardware with dynamic memory abstraction
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IWMM
2004
Springer
101views Hardware» more  IWMM 2004»
15 years 3 months ago
Exploring the barrier to entry: incremental generational garbage collection for Haskell
We document the design and implementation of a “production” incremental garbage collector for GHC 6.2. It builds on our earlier work (Non-stop Haskell) that exploited GHC’s ...
Andrew M. Cheadle, A. J. Field, Simon Marlow, Simo...
DATE
2006
IEEE
135views Hardware» more  DATE 2006»
15 years 3 months ago
FPGA architecture characterization for system level performance analysis
We present a modular and scalable approach for automatically extracting actual performance information from a set of FPGA-based architecture topologies. This information is used d...
Douglas Densmore, Adam Donlin, Alberto L. Sangiova...
ICCAD
2002
IEEE
94views Hardware» more  ICCAD 2002»
15 years 6 months ago
High-level synthesis of distributed logic-memory architectures
Abstract— With the increasing cost of global communication onchip, high-performance designs for data-intensive applications require architectures that distribute hardware resourc...
Chao Huang, Srivaths Ravi, Anand Raghunathan, Nira...
EUROPAR
2005
Springer
15 years 3 months ago
Event-Based Measurement and Analysis of One-Sided Communication
Abstract. To analyze the correctness and the performance of a program, information about the dynamic behavior of all participating processes is needed. The dynamic behavior can be ...
Marc-André Hermanns, Bernd Mohr, Felix Wolf
ASAP
2005
IEEE
165views Hardware» more  ASAP 2005»
15 years 3 months ago
CONAN - A Design Exploration Framework for Reliable Nano-Electronics
In this paper we introduce a design methodology that allows the system/circuit designer to build reliable systems out of unreliable nano-scale components. The central point of our...
Sorin Cotofana, Alexandre Schmid, Yusuf Leblebici,...