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» Designing hardware with dynamic memory abstraction
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ISLPED
2010
ACM
229views Hardware» more  ISLPED 2010»
14 years 9 months ago
An energy efficient cache design using spin torque transfer (STT) RAM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
Mitchelle Rasquinha, Dhruv Choudhary, Subho Chatte...
OOPSLA
2009
Springer
15 years 4 months ago
A concurrent dynamic analysis framework for multicore hardware
Software has spent the bounty of Moore’s law by solving harder problems and exploiting abstractions, such as highlevel languages, virtual machine technology, binary rewritdynami...
Jungwoo Ha, Matthew Arnold, Stephen M. Blackburn, ...
ASPLOS
2010
ACM
15 years 4 months ago
Specifying and dynamically verifying address translation-aware memory consistency
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciï...
Bogdan F. Romanescu, Alvin R. Lebeck, Daniel J. So...
USENIX
2003
14 years 11 months ago
Design and Implementation of Power-Aware Virtual Memory
Despite constant improvements in fabrication technology, hardware components are consuming more power than ever. With the everincreasing demand for higher performance in highly-in...
Hai Huang, Padmanabhan Pillai, Kang G. Shin
ICCD
2006
IEEE
139views Hardware» more  ICCD 2006»
15 years 6 months ago
Perceptron Based Consumer Prediction in Shared-Memory Multiprocessors
Abstract— Recent research has shown that forwarding speculative data to other processors before it is requested can improve the performance of multiprocessor systems. The most re...
Sean Leventhal, Manoj Franklin