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ISMVL
2005
IEEE
107views Hardware» more  ISMVL 2005»
15 years 5 months ago
Multiple-Valued Caches for Power-Efficient Embedded Systems
In this paper, we propose three novel cache models using Multiple-Valued Logic (MVL) paradigm to reduce the cache data storage area and cache energy consumption for embedded syste...
Emre Özer, Resit Sendag, David Gregg
DAC
2008
ACM
16 years 22 days ago
DVFS in loop accelerators using BLADES
Hardware accelerators are common in embedded systems that have high performance requirements but must still operate within stringent energy constraints. To facilitate short time-t...
Ganesh S. Dasika, Shidhartha Das, Kevin Fan, Scott...
ISCAS
2006
IEEE
103views Hardware» more  ISCAS 2006»
15 years 5 months ago
A low-power geometric mapping co-processor for high-speed graphics application
Abstract— In this article we present a novel design of a lowpower geometric mapping co-processor that can be used for high-performance graphics system. The processor can carry ou...
S. Leeke, L. Maharatna
101
Voted
IWSOC
2005
IEEE
151views Hardware» more  IWSOC 2005»
15 years 5 months ago
A Low Area and Low Power Programmable Baseband Processor Architecture
A fully programmable radio baseband processor architecture is presented. The architecture is based on a DSP processor core and a number flexible accelerators, connected via a con...
Eric Tell, Anders Nilsson, Dake Liu
FMCAD
2006
Springer
15 years 3 months ago
Design for Verification of the PCI-X Bus
The importance of re-usable Intellectual Properties (IPs) cores is increasing due to the growing complexity of today's system-on-chip and the need for rapid prototyping. In th...
Haja Moinudeen, Ali Habibi, Sofiène Tahar