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    JSAC
    2008
    124views more  JSAC 2008»
    Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding
    13 years 6 months ago
    Design Tradeoffs and Hardware Architecture for Real-Time Iterative MIMO Detection using Sphere Decoding and LDPC Coding
    Download  www.ee.ucla.edu
    Abstract-- We explore the performance and hardware complexity tradeoffs associated with performing iterative multipleinput multiple-output (MIMO) detection using a sphere decoder a...
    Hyungjin Kim, Dong-U Lee, John D. Villasenor
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    ASPDAC
    2006
    ACM
    124views Hardware» more  ASPDAC 2006»
    Functional modeling techniques for efficient SW code generation of video codec applications
    14 years 7 days ago
    Functional modeling techniques for efficient SW code generation of video codec applications
    Download  www.cecs.uci.edu
    –Architectures with multiple programmable cores are becoming more attractive for video codec applications because they can provide highly concurrent computation and support multi...
    Sang-Il Han, Soo-Ik Chae, Ahmed Amine Jerraya
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    ASPDAC
    2006
    ACM
    122views Hardware» more  ASPDAC 2006»
    Reusable component IP design using refinement-based design environment
    14 years 7 days ago
    Reusable component IP design using refinement-based design environment
    Download  www.cecs.uci.edu
    - We propose a method of enhancing the reusability of the component IPs by separating communication and computation for a system function. In this approach, we assume that the comp...
    Sanggyu Park, Sang-yong Yoon, Soo-Ik Chae
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    VLSISP
    2008
    123views more  VLSISP 2008»
    Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
    13 years 6 months ago
    Implementation of a Coarse-Grained Reconfigurable Media Processor for AVC Decoder
    Download  trappist.elis.ugent.be
    ADRES (Architecture for Dynamically Reconfigurable Embedded Systems) is a templatized coarse-grained reconfigurable processor architecture. It targets at embedded applications whic...
    Bingfeng Mei, Bjorn De Sutter, Tom Vander Aa, M. W...
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    DELTA
    2006
    IEEE
    173views Information Technology» more  DELTA 2006»
    Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
    13 years 10 months ago
    Implementation of Four Real-Time Software Defined Receivers and a Space-Time Decoder using Xilinx Virtex 2 Pro Field Programmabl
    Download  ir.canterbury.ac.nz
    This paper describes the concept, architecture, development and demonstration of a real time, high performance, software defined 4-receiver system and a space time decoder to be i...
    Peter J. Green, Desmond P. Taylor
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