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» Designing systems-on-chip using cores
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DCC
2007
IEEE
16 years 27 days ago
Algorithms and Hardware Structures for Unobtrusive Real-Time Compression of Instruction and Data Address Traces
Instruction and data address traces are widely used by computer designers for quantitative evaluations of new architectures and workload characterization, as well as by software de...
Milena Milenkovic, Aleksandar Milenkovic, Martin B...
FPGA
2009
ACM
200views FPGA» more  FPGA 2009»
15 years 8 months ago
FPGA-based front-end electronics for positron emission tomography
Modern Field Programmable Gate Arrays (FPGAs) are capable of performing complex discrete signal processing algorithms with clock rates above 100MHz. This combined with FPGA’s lo...
Michael Haselman, Robert Miyaoka, Thomas K. Lewell...
HASKELL
2009
ACM
15 years 7 months ago
A compositional theory for STM Haskell
We address the problem of reasoning about Haskell programs that use Software Transactional Memory (STM). As a motivating example, we consider Haskell code for a concurrent non-det...
Johannes Borgström, Karthikeyan Bhargavan, An...
ANSS
2007
IEEE
15 years 7 months ago
JANE - The Java Ad Hoc Network Development Environment
This work describes a Java based development platform which is intended to support ad hoc network researchers in application and protocol design. Software development within this ...
Daniel Görgen, Hannes Frey, Christian Hiedels
ISPASS
2007
IEEE
15 years 7 months ago
CA-RAM: A High-Performance Memory Substrate for Search-Intensive Applications
This paper proposes a specialized memory structure called CA-RAM (Content Addressable Random Access Memory) to accelerate search operations present in many important real-world ap...
Sangyeun Cho, Joel R. Martin, Ruibin Xu, Mohammad ...