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» Designing systems-on-chip using cores
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FPL
2006
Springer
91views Hardware» more  FPL 2006»
15 years 5 months ago
Reconfigurable Systems Enabled by a Network-on-Chip
A modern SoC design comprises dozens of dedicated IP cores for specialized tasks and processors for generalpurpose tasks. Flexibility is the key feature of processors, since it is...
Leandro Möller, Ismael Grehs, Ney Calazans, F...
FPL
2003
Springer
128views Hardware» more  FPL 2003»
15 years 6 months ago
A Generic Architecture for Integrated Smart Transducers
Abstract. A smart transducer network hosts various nodes with different functionality. Our approach offers the possibility to design different smart transducer nodes as a system...
Martin Delvai, Ulrike Eisenmann, Wilfried Elmenrei...
DATE
2007
IEEE
100views Hardware» more  DATE 2007»
15 years 7 months ago
SoC testing using LFSR reseeding, and scan-slice-based TAM optimization and test scheduling
Abstract— We present an SoC testing approach that integrates test data compression, TAM/test wrapper design, and test scheduling. An improved LFSR reseeding technique is used as ...
Zhanglei Wang, Krishnendu Chakrabarty, Seongmoon W...
MSE
2005
IEEE
153views Hardware» more  MSE 2005»
15 years 7 months ago
ipPROCESS: Using a Process to Teach IP-Core Development
The reusing of Intellectual Property cores has been an alternative to the increasing gap between design productivity and chip complexity of emerging System-on-chip (SoC) designs. ...
Marilia Lima, Andre Aziz, Diogo José Costa ...
DFT
2006
IEEE
203views VLSI» more  DFT 2006»
15 years 7 months ago
Self Testing SoC with Reduced Memory Requirements and Minimized Hardware Overhead
This paper describes a methodology of creating a built-in diagnostic system of a System on Chip and experimental results of the system application on the AT94K FPSLIC with cores d...
Ondrej Novák, Zdenek Plíva, Jiri Jen...