1226 search results - page 65 / 246 » Designing systems-on-chip using cores |
VTS
2006
IEEE
2006
IEEE
Combining Linear and Non-Linear Test Vector Compression Using Correlation-Based Rectangular Encoding
15 years 7 months ago
A technique is presented here for improving the compression achieved with any linear decompressor by adding a small non-linear decoder that exploits bit-wise and pattern-wise corr...
IJES
2008
15 years 1 months ago
2008
: Current and future SoC designs will contain an increasing number of programmable units. To be able to tailor and debug these processors in their system context at the highest pos...
219
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CODES
2011
IEEE
14 years 1 months ago
2011
IEEE
The trend towards many-core systems comes with various issues, among them their highly dynamic and non-predictable workloads. Hence, new paradigms for managing resources of many-c...
134
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VLSID
2004
IEEE
16 years 1 months ago
2004
IEEE
As chip complexity grows, design productivity boost is expected from reuse of large parts and blocks of previous designs with the design effort largely invested into the new parts...
IISWC
2009
IEEE
15 years 8 months ago
2009
IEEE
PARSEC is a reference application suite used in industry and academia to assess new Chip Multiprocessor (CMP) designs. No investigation to date has profiled PARSEC on real hardwa...