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» Designing systems-on-chip using cores
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ASYNC
2003
IEEE
72views Hardware» more  ASYNC 2003»
15 years 6 months ago
SNAP: A Sensor-Network Asynchronous Processor
We present a Sensor-Network Asynchronous Processor (SNAP), which we have designed to be both a processor core for a sensor-network node and a component of a chip multiprocessor, t...
Clinton Kelly IV, Virantha N. Ekanayake, Rajit Man...
IAT
2003
IEEE
15 years 6 months ago
Multi-agent Technology for Distributed Data Mining and Classification
The core problem of multi-agent distributed data mining technology not concern particular data mining techniques although the latter is now paid the most attention. Its core probl...
Vladimir Gorodetsky, Oleg Karsaev, Vladimir Samoil...
FPL
2009
Springer
101views Hardware» more  FPL 2009»
15 years 6 months ago
An accelerator for K-TH nearest neighbor thinning based on the IMORC infrastructure
The creation and optimization of FPGA accelerators comprising several compute cores and memories are challenging tasks in high performance reconfigurable computing. In this paper...
Tobias Schumacher, Christian Plessl, Marco Platzne...
ISCA
2007
IEEE
146views Hardware» more  ISCA 2007»
15 years 7 months ago
Automated design of application specific superscalar processors: an analytical approach
Analytical modeling is applied to the automated design of application-specific superscalar processors. Using an analytical method bridges the gap between the size of the design sp...
Tejas Karkhanis, James E. Smith
ASPLOS
2004
ACM
15 years 6 months ago
Heat-and-run: leveraging SMT and CMP to manage power density through the operating system
Power density in high-performance processors continues to increase with technology generations as scaling of current, clock speed, and device density outpaces the downscaling of s...
Mohamed A. Gomaa, Michael D. Powell, T. N. Vijayku...