1226 search results - page 82 / 246 » Designing systems-on-chip using cores |
110
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ET
2002
15 years 1 months ago
2002
Test access mechanisms (TAMs) and test wrappers are integral parts of a system-on-chip (SOC) test architecture. Prior research has concentrated on only one aspect of the TAM/wrappe...
121
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SEFM
2005
IEEE
15 years 7 months ago
2005
IEEE
The need for the B method first appeared in industry, and several commercial tools have been developed to support this formalism. However, few of these tools allow reasoning on t...
117
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IPPS
2000
IEEE
15 years 5 months ago
2000
IEEE
JRoute is a set of Java classes that provide an application programming interface (API) for routing of Xilinx FPGA devices. The interface allows various levels of control from conn...
122
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MICRO
2009
IEEE
15 years 8 months ago
2009
IEEE
A key challenge in architecting a CMP with many cores is maintaining cache coherence in an efficient manner. Directory-based protocols avoid the bandwidth overhead of snoop-based ...
117
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CF
2008
ACM
15 years 3 months ago
2008
ACM
The current methodology used in mass-market processor design is to create a single base microarchitecture (e.g., Intel's "Core"or AMD's"K8") that is ...