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ISCA
2009
IEEE
148views Hardware» more  ISCA 2009»
15 years 4 months ago
Memory mapped ECC: low-cost error protection for last level caches
This paper presents a novel technique, Memory Mapped ECC, which reduces the cost of providing error correction for SRAM caches. It is important to limit such overheads as processo...
Doe Hyun Yoon, Mattan Erez
CASES
2006
ACM
15 years 1 months ago
Cost-efficient soft error protection for embedded microprocessors
Device scaling trends dramatically increase the susceptibility of microprocessors to soft errors. Further, mounting demand for embedded microprocessors in a wide array of safety c...
Jason A. Blome, Shantanu Gupta, Shuguang Feng, Sco...
USS
2008
15 years 8 days ago
Panalyst: Privacy-Aware Remote Error Analysis on Commodity Software
Remote error analysis aims at timely detection and remedy of software vulnerabilities through analyzing runtime errors that occur on the client. This objective can only be achieve...
Rui Wang 0010, XiaoFeng Wang, Zhuowei Li
ASPLOS
2010
ACM
15 years 4 months ago
Shoestring: probabilistic soft error reliability on the cheap
Aggressive technology scaling provides designers with an ever increasing budget of cheaper and faster transistors. Unfortunately, this trend is accompanied by a decline in individ...
Shuguang Feng, Shantanu Gupta, Amin Ansari, Scott ...
IESS
2007
Springer
120views Hardware» more  IESS 2007»
15 years 4 months ago
Error Containment in the Time-Triggered System-On-a-Chip Architecture
Abstract: The time-triggered System-on-a-Chip (SoC) architecture provides a generic multicore system platform for a family of composable and dependable giga-scale SoCs. It supports...
Roman Obermaisser, Hermann Kopetz, Christian El Sa...