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JSS
2006
104views more  JSS 2006»
14 years 9 months ago
Modelling and simulation of off-chip communication architectures for high-speed packet processors
In this work, we propose a visual, custom-designed, event-driven interconnect simulation framework to evaluate the performance of off-chip multi-processor/memory communications ar...
Jacob Engel, Daniel Lacks, Taskin Koçak
ISCAS
2007
IEEE
123views Hardware» more  ISCAS 2007»
15 years 3 months ago
Evaluating Network-on-Chip for Homogeneous Embedded Multiprocessors in FPGAs
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
Henrique C. Freitas, Dalton M. Colombo, Fernanda L...
NETWORKING
2004
14 years 11 months ago
On the Feasibility of Integrated MPEG Teleconference and Data Transmission, over IEEE 802.11 WLANs
The most widespread Wireless Local Area Networks (WLANs) are based today on the IEEE 802.11 standard and its various versions, especially the IEEE 802.11b. In this article we first...
Ioannis Broustis, Michael Paterakis
62
Voted
DATE
2009
IEEE
81views Hardware» more  DATE 2009»
15 years 4 months ago
ReSim, a trace-driven, reconfigurable ILP processor simulator
— Modern processors are becoming more complex and as features and application size increase, their evaluation is becoming more time-consuming. To date, design space exploration r...
Sotiria Fytraki, Dionisios N. Pnevmatikatos
83
Voted
ICDE
2009
IEEE
171views Database» more  ICDE 2009»
15 years 4 months ago
CoTS: A Scalable Framework for Parallelizing Frequency Counting over Data Streams
Applications involving analysis of data streams have gained significant popularity and importance. Frequency counting, frequent elements and top-k queries form a class of operato...
Sudipto Das, Shyam Antony, Divyakant Agrawal, Amr ...