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CAV
2000
Springer
89views Hardware» more  CAV 2000»
15 years 4 months ago
Tuning SAT Checkers for Bounded Model Checking
Abstract. Bounded Model Checking based on SAT methods has recently been introduced as a complementary technique to BDD-based Symbolic Model Checking. The basic idea is to search fo...
Ofer Strichman
101
Voted
VLSID
1999
IEEE
122views VLSI» more  VLSID 1999»
15 years 4 months ago
Formal Verification of an ARM Processor
This paper presents a detailed description of the application of a formal verification methodology to an ARM processor. The processor, a hybrid between the ARM7 and the StrongARM ...
Vishnu A. Patankar, Alok Jain, Randal E. Bryant
IPPS
1998
IEEE
15 years 4 months ago
Processor Lower Bound Formulas for Array Computations and Parametric Diophantine Systems
Using a directed acyclic graph (dag) model of algorithms, we solve a problem related to precedenceconstrained multiprocessor schedules for array computations: Given a sequence of ...
Peter R. Cappello, Ömer Egecioglu
78
Voted
DAC
1996
ACM
15 years 4 months ago
Power Estimation of Cell-Based CMOS Circuits
PPP is a Web-based simulation and synthesis environment for low-power design. In this paper we describe the gate-level simulation engine of PPP, that achieves accuracy always with...
Alessandro Bogliolo, Luca Benini, Bruno Ricc&ograv...
114
Voted
AIIA
2007
Springer
15 years 4 months ago
Mobile Robots and Intelligent Environments
Abstract-- This paper deals with an architecture for knowledge representation suitable for integrated Robotics and Ambient Intelligence applications. The aim of the work is to adop...
Francesco Capezio, Fulvio Mastrogiovanni, Antonio ...