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IPPS
1998
IEEE
15 years 1 months ago
Design, Implementation and Evaluation of Parallel Pipelined STAP on Parallel Computers
This paper presents performance results for the design and implementation of parallel pipelined Space-Time Adaptive Processing (STAP) algorithms on parallel computers. In particul...
Alok N. Choudhary, Wei-keng Liao, Donald Weiner, P...
CODES
2005
IEEE
15 years 3 months ago
High-level synthesis for large bit-width multipliers on FPGAs: a case study
In this paper, we present the analysis, design and implementation of an estimator to realize large bit width unsigned integer multiplier units. Larger multiplier units are require...
Gang Quan, James P. Davis, Siddhaveerasharan Devar...
ADHOC
2011
14 years 4 months ago
Design and analysis of a propagation delay tolerant ALOHA protocol for underwater networks
Acoustic underwater wireless sensor networks (UWSN) have recently gained attention as a topic of research. Such networks are characterized by increased uncertainty in medium acces...
Joon Ahn, Affan A. Syed, Bhaskar Krishnamachari, J...
CLUSTER
2009
IEEE
15 years 2 months ago
Finding a tradeoff between host interrupt load and MPI latency over Ethernet
—Achieving high-performance message passing on top of generic ETHERNET hardware suffers from the NIC interruptdriven model where coalescing is usually involved. We present an in-...
Brice Goglin, Nathalie Furmento
75
Voted
ICS
2005
Tsinghua U.
15 years 3 months ago
Reducing latencies of pipelined cache accesses through set prediction
With the increasing performance gap between the processor and the memory, the importance of caches is increasing for high performance processors. However, with reducing feature si...
Aneesh Aggarwal