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153
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IPPS
2006
IEEE
15 years 10 months ago
Reducing the associativity and size of step caches in CRCW operation
Step caches are caches in which data entered to an cache array is kept valid only until the end of ongoing step of execution. Together with an advanced pipelined multithreaded arc...
M. Forsell
DEBS
2007
ACM
15 years 8 months ago
Scalable event matching for overlapping subscriptions in pub/sub systems
Content-based publish/subscribe systems allow matching the content of events with predicates in the subscriptions. However, most existing systems only allow a limited set of opera...
Zhen Liu, Srinivasan Parthasarathy 0002, Anand Ran...
COLCOM
2005
IEEE
15 years 10 months ago
Maintaining multi-way dataflow constraints in collaborative systems
Multi-way dataflow constraints are very useful in the development of collaborative applications, such as collaborative CAD and CASE systems, but satisfying multi-way dataflow cons...
Kai Lin, David Chen, R. Geoff Dromey, Chengzheng S...
HPCA
1995
IEEE
15 years 8 months ago
Program Balance and Its Impact on High Performance RISC Architectures
Information on the behavior of programs is essential for deciding the number and nature of functional units in high performance architectures. In this paper, we present studies on...
Lizy Kurian John, Vinod Reddy, Paul T. Hulina, Lee...
141
Voted
IPPS
2007
IEEE
15 years 11 months ago
A General Purpose Partially Reconfigurable Processor Simulator (PReProS)
An innovative technique to model and simulate partial and dynamic reconfigurable processors is presented in this paper. The basis for development is a SystemC kernel modified for ...
Alisson Vasconcelos De Brito, Matthias Kühnle...