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IPPS
2000
IEEE
15 years 9 months ago
The Memory Bandwidth Bottleneck and its Amelioration by a Compiler
As the speed gap between CPU and memory widens, memory hierarchy has become the primary factor limiting program performance. Until now, the principal focus of hardware and softwar...
Chen Ding, Ken Kennedy
IPPS
2000
IEEE
15 years 9 months ago
Replicating the Contents of a WWW Multimedia Repository to Minimize Download Time
Dynamic replication algorithms aim at allocating, migrating and deleting copies of an object over various Internet hosts, according to the access patterns exhibited online, so as ...
Thanasis Loukopoulos, Ishfaq Ahmad
IPPS
2000
IEEE
15 years 9 months ago
Ordering Unstructured Meshes for Sparse Matrix Computations on Leading Parallel Systems
Abstract. Computer simulations of realistic applications usually require solving a set of non-linear partial di erential equations PDEs over a nite region. The process of obtaini...
Leonid Oliker, Xiaoye S. Li, Gerd Heber, Rupak Bis...
IPPS
2000
IEEE
15 years 9 months ago
On the Scheduling Algorithm of the Dynamically Trace Scheduled VLIW Architecture
In a machine that follows the dynamically trace scheduled VLIW (DTSVLIW) architecture, VLIW instructions are built dynamically through an algorithm that can be implemented in hard...
Alberto Ferreira de Souza, Peter Rounce
PPOPP
1999
ACM
15 years 9 months ago
Automatic Parallelization of Divide and Conquer Algorithms
Divide and conquer algorithms are a good match for modern parallel machines: they tend to have large amounts of inherent parallelism and they work well with caches and deep memory...
Radu Rugina, Martin C. Rinard