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ICCAD
2006
IEEE
101views Hardware» more  ICCAD 2006»
15 years 11 months ago
Thermal-induced leakage power optimization by redundant resource allocation
Traditionally, at early design stages, leakage power is associated with the number of transistors in a design. Hence, intuitively an implementation with minimum resource usage wou...
Min Ni, Seda Ogrenci Memik
139
Voted
IEEEPACT
2006
IEEE
15 years 11 months ago
Overlapping dependent loads with addressless preload
Modern out-of-order processors with non-blocking caches exploit Memory-Level Parallelism (MLP) by overlapping cache misses in a wide instruction window. The exploitation of MLP, h...
Zhen Yang, Xudong Shi, Feiqi Su, Jih-Kwon Peir
MICRO
2006
IEEE
145views Hardware» more  MICRO 2006»
15 years 11 months ago
A Floorplan-Aware Dynamic Inductive Noise Controller for Reliable Processor Design
Power delivery is a growing reliability concern in microprocessors as the industry moves toward feature-rich, powerhungrier designs. To battle the ever-aggravating power consumpti...
Fayez Mohamood, Michael B. Healy, Sung Kyu Lim, Hs...
ASPLOS
2006
ACM
15 years 11 months ago
A spatial path scheduling algorithm for EDGE architectures
Growing on-chip wire delays are motivating architectural features that expose on-chip communication to the compiler. EDGE architectures are one example of communication-exposed mi...
Katherine E. Coons, Xia Chen, Doug Burger, Kathryn...
SAC
2006
ACM
15 years 11 months ago
Mining and analyzing the topological structure of protein-protein interaction networks
We report a comprehensive evaluation of the topological structure of protein-protein interaction (PPI) networks by mining and analyzing graphs constructed from the publicly availa...
Daniel Duanqing Wu, Xiaohua Hu