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» Distributed sleep transistor network for power reduction
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DFT
2006
IEEE
143views VLSI» more  DFT 2006»
15 years 3 months ago
Defect Tolerant and Energy Economized DSP Plane of a 3-D Heterogeneous SoC
This paper1 discusses a defect tolerant and energy economized computing array for the DSP plane of a 3-D Heterogeneous System on a Chip. We present the J-platform, which employs c...
Vijay K. Jain, Glenn H. Chapman
HPCC
2007
Springer
15 years 1 months ago
Power-Aware Fat-Tree Networks Using On/Off Links
Abstract. Nowadays, power consumption reduction techniques are being increasingly used in computer systems, and high-performance computing systems are not an exception. In particul...
Marina Alonso, Salvador Coll, Vicente Santonja, Ju...
GLVLSI
2009
IEEE
123views VLSI» more  GLVLSI 2009»
15 years 4 months ago
Power efficient tree-based crosslinks for skew reduction
Clock distribution networks are an important design issue that is highly dependent on delay variations and load imbalances, while requiring power efficiency. Existing mesh solutio...
Inna Vaisband, Ran Ginosar, Avinoam Kolodny, Eby G...
VTC
2007
IEEE
198views Communications» more  VTC 2007»
15 years 3 months ago
A Distributed Node Scheduling Protocol Considering Sensing Coverage in Wireless Sensor Networks
Abstract— A crucial issue in deploying wireless sensor networks is to perform a sensing task in an area of interest in an energy-efficient manner since sensor nodes have limited...
Jaekyu Cho, Gilsoo Kim, Taekyoung Kwon, Yanghee Ch...
MOBISYS
2005
ACM
15 years 9 months ago
Turducken: hierarchical power management for mobile devices
Abstract-Maintaining optimal consistency in a distributed system requires that nodes be always-on to synchronize information. Unfortunately, mobile devices such as laptops do not h...
Jacob Sorber, Nilanjan Banerjee, Mark D. Corner, S...