7379 search results - page 1017 / 1476 » Distributed vector architectures |
132
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VLSID
2005
IEEE
16 years 6 months ago
2005
IEEE
Timing margin (slack) needs to be carefully managed to ensure a satisfactory timing yield. We propose a new design flow that combines a false-path-aware gate sizing and a statisti...
155
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VLSID
2003
IEEE
16 years 6 months ago
2003
IEEE
Exploitation of silicon capacity will require improvements in design productivity and more scalable system paradigms. Asynchronous message passing networks on chip (NOC) have been...
161
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VLSID
2001
IEEE
16 years 6 months ago
2001
IEEE
A technique for signature based diagnosis using windows of different sizes is presented. It allows to obtain increased diagnostic information from a given test at a lower cost, wi...
185
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HPCA
2008
IEEE
16 years 6 months ago
2008
IEEE
This paper describes a comprehensive approach for using the memory controller to improve DRAM energy efficiency and manage DRAM power. We make three contributions: (1) we describe...
137
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HPCA
2008
IEEE
16 years 6 months ago
2008
IEEE
Recent advances in statistical inference and machine learning close the divide between simulation and classical optimization, thereby enabling more rigorous and robust microarchit...