7379 search results - page 3 / 1476 » Distributed vector architectures |
CATA
2004
15 years 1 months ago
2004
This paper describes the instruction execution mechanism of Responsive Multithreaded (RMT) Processor for distributed real-time processing. The execution order of each thread is co...
117
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ICPP
2009
IEEE
15 years 6 months ago
2009
IEEE
—Sparse Matrix-Vector multiplication (SpMV) is a very challenging computational kernel, since its performance depends greatly on both the input matrix and the underlying architec...
153
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PARLE
1994
15 years 3 months ago
1994
Sparse matrix-vector multiplication forms the heart of iterative linear solvers used widely in scientific computations (e.g., finite element methods). In such solvers, the matrix-v...
ISPAN
2009
IEEE
15 years 6 months ago
2009
IEEE
—In this paper, we present a design architecture of implementing a ”Vector Bank” into video encoder system, namely, an H.264 encoder, in order to detect and analyze the movin...
IPPS
2005
IEEE
15 years 5 months ago
2005
IEEE
Multimedia extensions (MME) are architectural extensions to general-purpose processors to boost the performance of multimedia workloads. Today, in-line assembly code, intrinsic fu...