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MTDT
2006
IEEE
154views Hardware» more  MTDT 2006»
15 years 7 months ago
SRAM Cell Current in Low Leakage Design
This paper highlights the cell current characterization of a low leakage 6T SRAM by adjusting the threshold voltages of the transistors in the memory array to reduce the standby p...
Ding-Ming Kwai, Ching-Hua Hsiao, Chung-Ping Kuo, C...
110
Voted
RTSS
2006
IEEE
15 years 7 months ago
Processor Scheduler for Multi-Service Routers
In this paper, we describe the design and evaluation of a scheduler (referred to as Everest) for allocating processors to services in high performance, multi-service routers. A sc...
Ravi Kokku, Upendra Shevade, Nishit Shah, Ajay Mah...
SCAM
2006
IEEE
15 years 7 months ago
Constructing Accurate Application Call Graphs For Java To Model Library Callbacks
Call graphs are widely used to represent calling relationships among methods. However, there is not much interest in calling relationships among library methods in many software e...
Weilei Zhang, Barbara G. Ryder
VTS
2006
IEEE
133views Hardware» more  VTS 2006»
15 years 7 months ago
PEAKASO: Peak-Temperature Aware Scan-Vector Optimization
— In this paper, an algorithm for scan vector ordering, PEAKASO, is proposed to minimize the peak temperature during scan testing. Given a circuit with scan and the scan vectors,...
Minsik Cho, David Z. Pan
92
Voted
ASPDAC
2006
ACM
104views Hardware» more  ASPDAC 2006»
15 years 7 months ago
A multi-technology-process reticle floorplanner and wafer dicing planner for multi-project wafers
—As the VLSI manufacturing technology advances into the deep sub-micron(DSM) era, the mask cost can reach one or two million dollars. Multiple project wafers (MPW) which put diï¬...
Chien-Chang Chen, Wai-Kei Mak