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ICCAD
2006
IEEE
141views Hardware» more  ICCAD 2006»
15 years 8 months ago
A code refinement methodology for performance-improved synthesis from C
Although many recent advances have been made in hardware synthesis techniques from software programming languages such as C, the performance of synthesized hardware commonly suffe...
Greg Stitt, Frank Vahid, Walid A. Najjar
ICCAD
2004
IEEE
158views Hardware» more  ICCAD 2004»
15 years 8 months ago
DAOmap: a depth-optimal area optimization mapping algorithm for FPGA designs
In this paper we study the technology mapping problem for FPGA architectures to minimize chip area, or the total number of lookup tables (LUTs) of the mapped design, under the chi...
Deming Chen, Jason Cong
CGO
2010
IEEE
15 years 6 months ago
Automated just-in-time compiler tuning
Managed runtime systems, such as a Java virtual machine (JVM), are complex pieces of software with many interacting components. The Just-In-Time (JIT) compiler is at the core of t...
Kenneth Hoste, Andy Georges, Lieven Eeckhout
ISPD
2010
ACM
217views Hardware» more  ISPD 2010»
15 years 6 months ago
ITOP: integrating timing optimization within placement
Timing-driven placement is a critical step in nanometerscale physical synthesis. To improve design timing on a global scale, net-weight based global timing-driven placement is a c...
Natarajan Viswanathan, Gi-Joon Nam, Jarrod A. Roy,...
ISPD
2010
ACM
163views Hardware» more  ISPD 2010»
15 years 6 months ago
A statistical framework for designing on-chip thermal sensing infrastructure in nano-scale systems
Thermal/power issues have become increasingly important with more and more transistors being put on a single chip. Many dynamic thermal/power management techniques have been propo...
Yufu Zhang, Bing Shi, Ankur Srivastava