473 search results - page 25 / 95 » Dynamic Memory Design for Low Data-Retention Power |
111
Voted
ICCD
2006
IEEE
16 years 18 days ago
2006
IEEE
Abstract— Timing and low power emerge as the most important goals in contemporary design. Meanwhile, the majority of placement algorithms developed by industry and academia still...
121
Voted
MICRO
2000
IEEE
15 years 7 months ago
2000
IEEE
Data, addresses, and instructions are compressed by maintaining only significant bytes with two or three extension bits appended to indicate the significant byte positions. This s...
131
Voted
ISLPED
2010
ACM
15 years 3 months ago
2010
ACM
The on-chip memory is a dominant source of power and energy consumption in modern and future processors. This paper explores the use of a new emerging non-volatile memory technolo...
122
Voted
ISLPED
2003
ACM
15 years 9 months ago
2003
ACM
Tag comparison elimination (TCE) is an effective approach to reduce I-cache energy. Current research focuses on finding good tradeoffs between hardware cost and percentage of comp...
121
Voted
DAC
1999
ACM
16 years 4 months ago
1999
ACM
We present a framework for rapidly exploring the design space of low power application-specific programmable processors (ASPP), in particular mediaprocessors. We focus on a catego...