989 search results - page 122 / 198 » Dynamic Symmetry Reduction |
154
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FPGA
2007
ACM
15 years 10 months ago
2007
ACM
Power consumption in field programmable gate arrays (FPGAs) has become an important issue as the FPGA market has grown to include mobile platforms. In this work we present a power...
108
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GLVLSI
2006
IEEE
15 years 10 months ago
2006
IEEE
This paper presents a minimum area, low-power driven clustering algorithm for coarse-grained, antifuse-based FPGAs under delay constraints. The algorithm accurately predicts logic...
112
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GLVLSI
2005
IEEE
15 years 10 months ago
2005
IEEE
The ever-increasing number of transistors on a chip has resulted in very large scale integration (VLSI) systems whose performance and manufacturing costs are driven by on-chip wir...
135
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ISCAS
2005
IEEE
15 years 10 months ago
2005
IEEE
— In this paper we explore the relationship between power and area. By exploiting parallelism (and thus using more area) one can reduce the switching frequency allowing a reducti...
116
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ASPDAC
2005
ACM
15 years 10 months ago
2005
ACM
— The recent popularity of 3D IC technology stems from its enhanced performance capabilities and reduced wirelength. However, wire congestion and thermal issues are exacerbated d...