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ISSS
1998
IEEE
120views Hardware» more  ISSS 1998»
15 years 4 months ago
Application of Instruction Analysis/Synthesis Tools to x86's Functional Unit Allocation
Designing a cost effective superscalar architecture for x86 compatible microprocessors is a challenging task in terms of both technical difficulty and commercial value. One of the...
Ing-Jer Huang, Ping-Huei Xie
KBSE
2006
IEEE
15 years 5 months ago
Managing the Complexity of Large Free and Open Source Package-Based Software Distributions
The widespread adoption of Free and Open Source Software (FOSS) in many strategic contexts of the information technology society has drawn the attention on the issues regarding ho...
Fabio Mancinelli, Jaap Boender, Roberto Di Cosmo, ...
IPPS
2007
IEEE
15 years 6 months ago
Radiation Hardened Coarse-Grain Reconfigurable Architecture for Space Applications
Technology trends are such that single event effects (SEE)are likely to become even more of a concern for the future. Decreasing feature sizes, lower operating voltage, and higher...
Sajid Baloch, Tughrul Arslan, Adrian Stoica
ICPP
2003
IEEE
15 years 5 months ago
Procedural Level Address Offset Assignment of DSP Applications with Loops
Automatic optimization of address offset assignment for DSP applications, which reduces the number of address arithmetic instructions to meet the tight memory size restrictions an...
Youtao Zhang, Jun Yang 0002
ISHPC
1999
Springer
15 years 4 months ago
Instruction-Level Microprocessor Modeling of Scientific Applications
Superscalar microprocessor efficiency is generally not as high as anticipated. In fact, sustained utilization below thirty percent of peak is not uncommon, even for fully optimized...
Kirk W. Cameron, Yong Luo, James Scharzmeier