283 search results - page 20 / 57 » Effective Program Verification for Relaxed Memory Models |
180
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POPL
2003
ACM
15 years 12 months ago
2003
ACM
We present the design of a typed assembly language called TALT that supports heterogeneous tuples, disjoint sums, and a general account of addressing modes. TALT also implements t...
111
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EMSOFT
2006
Springer
15 years 1 months ago
2006
Springer
Distributed real-time and embedded (DRE) systems have stringent constraints on timeliness and other properties whose assurance is crucial to correct system behavior. Formal tools ...
ASPLOS
2010
ACM
15 years 6 months ago
2010
ACM
Computer systems with virtual memory are susceptible to design bugs and runtime faults in their address translation (AT) systems. Detecting bugs and faults requires a clear speciï...
100
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SBACPAD
2008
IEEE
15 years 6 months ago
2008
IEEE
Transactional memory is emerging as a parallel programming paradigm for multi-core processors. Despite the recent interest in transactional memory, there has been no study to char...
104
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TPDS
1998
14 years 11 months ago
1998
This paper presents a new compiler optimization algorithm that parallelizes applications for symmetric, sharedmemory multiprocessors. The algorithm considers data locality, parall...