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» Efficient Coupling of Parallel Applications Using PAWS
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HPCA
2001
IEEE
16 years 26 days ago
Automatically Mapping Code on an Intelligent Memory Architecture
This paper presents an algorithm to automatically map code on a generic intelligent memory system that consists of a host processor and a simpler memory processor. To achieve high...
Jaejin Lee, Yan Solihin, Josep Torrellas
114
Voted
SMA
2008
ACM
149views Solid Modeling» more  SMA 2008»
15 years 13 days ago
Exact arrangements on tori and Dupin cyclides
An algorithm and implementation is presented to compute the exact arrangement induced by arbitrary algebraic surfaces on a parametrized ring Dupin cyclide. The family of Dupin cyc...
Eric Berberich, Michael Kerber
MICRO
2008
IEEE
118views Hardware» more  MICRO 2008»
15 years 7 months ago
Notary: Hardware techniques to enhance signatures
Hardware signatures have been recently proposed as an efficient mechanism to detect conflicts amongst concurrently running transactions in transactional memory systems (e.g., Bulk...
Luke Yen, Stark C. Draper, Mark D. Hill
115
Voted
HPCA
2009
IEEE
15 years 7 months ago
Reconciling specialization and flexibility through compound circuits
While parallelism and multi-cores are receiving much attention as a major scalability path, customization is another, orthogonal and complementary, scalability path which can targ...
Sami Yehia, Sylvain Girbal, Hugues Berry, Olivier ...
MICRO
2010
IEEE
153views Hardware» more  MICRO 2010»
14 years 10 months ago
Throughput-Effective On-Chip Networks for Manycore Accelerators
As the number of cores and threads in manycore compute accelerators such as Graphics Processing Units (GPU) increases, so does the importance of on-chip interconnection network des...
Ali Bakhoda, John Kim, Tor M. Aamodt