214 search results - page 17 / 43 » Efficient bump mapping hardware |
VVS
1996
IEEE
15 years 1 months ago
1996
IEEE
A new and easy-to-implement method for direct volume rendering that uses 3D texture maps for acceleration, and incorporates directional lighting, is described. The implementation,...
113
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ICCD
2007
IEEE
15 years 1 months ago
2007
IEEE
In this paper we propose techniques to dynamically downsize or upsize a cache accompanied by cache set/line shutdown to produce efficient caches. Unlike previous approaches, resiz...
MICRO
1997
IEEE
15 years 1 months ago
1997
IEEE
Most modern microprocessors employ one or two levels of on-chip caches in order to improve performance. These caches are typically implemented with static RAM cells and often occu...
FPL
2009
Springer
15 years 1 months ago
2009
Springer
The acceleration of molecular dynamics (MD) simulations using high performance reconfigurable computing (HPRC) has been much studied. Given the intense competition from multicore...
109
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DATE
2009
IEEE
15 years 1 months ago
2009
IEEE
The inherent reconfigurability of SRAM-based FPGAs enables the use of configurations optimized for the problem at hand. Optimized configurations are smaller and faster than their g...