544 search results - page 46 / 109 » Efficient checker processor design |
DAC
1996
ACM
15 years 1 months ago
1996
ACM
This paper discusses the design of a chip using architectural synthesis. The chip, FADIC, is applied in Digital Audio Broadcasting (DAB) receivers. It shows that architectural syn...
DAC
2002
ACM
15 years 10 months ago
2002
ACM
In this paper, we present a flexible accelerator designed for networking applications. The accelerator can be utilized efficiently by a variety of Network Processor designs. Most ...
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CODES
2010
IEEE
14 years 7 months ago
2010
IEEE
With the continuous scaling of semiconductor technology, the life-time of circuit is decreasing so that processor failure becomes an important issue in MPSoC design. A software so...
FPL
2008
Springer
14 years 11 months ago
2008
Springer
For the next generation of multi-core processors, the onchip interconnection networks must be efficient to achieve high data throughput and performance. Moreover, these interconne...
IAJIT
2010
14 years 8 months ago
2010
: A new code sign implementation of vector median rational hybrid filter based on efficient hardware/software implementation is introduced and applied to colour image filtering pro...