544 search results - page 49 / 109 » Efficient checker processor design |
ICIP
2007
IEEE
15 years 4 months ago
2007
IEEE
This paper presents some techniques for efficient motion estimation (ME) implementation on fixed-point digital signal processor (DSP) for high resolution video coding. First, chal...
HEURISTICS
2000
14 years 9 months ago
2000
Planning and designing the next generation of IP router or switched broadband networks seems a daunting challenge considering the many complex, interacting factors affecting the p...
ANCS
2008
ACM
14 years 11 months ago
2008
ACM
Computer networks require increasingly complex packet processing in the data path to adapt to new functionality requirements. To meet performance demands, packet processing system...
JEC
2006
14 years 9 months ago
2006
We present an overview of the Synchroscalar single-chip, multi-core processor. Through the design of Synchroscalar, we find that high energy efficiency and low complexity can be a...
CASES
2008
ACM
14 years 11 months ago
2008
ACM
In this paper, we introduce Optimus: an optimizing synthesis compiler for streaming applications. Optimus compiles programs written in a high level streaming language to either so...