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» Efficient checker processor design
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DAC
1996
ACM
15 years 1 months ago
Address Calculation for Retargetable Compilation and Exploration of Instruction-Set Architectures
The advent of parallel executing Address Calculation Units (ACUs) in Digital Signal Processor (DSP) and Application Specific InstructionSet Processor (ASIP) architectures has made...
Clifford Liem, Pierre G. Paulin, Ahmed Amine Jerra...
WAE
2001
281views Algorithms» more  WAE 2001»
14 years 11 months ago
Using PRAM Algorithms on a Uniform-Memory-Access Shared-Memory Architecture
The ability to provide uniform shared-memory access to a significant number of processors in a single SMP node brings us much closer to the ideal PRAM parallel computer. In this pa...
David A. Bader, Ajith K. Illendula, Bernard M. E. ...
MST
2000
101views more  MST 2000»
14 years 9 months ago
Robust Parallel Computations through Randomization
In this paper we present an efficient general simulation strategy for computations designed for fully operational BSP machines of n ideal processors, on n-processor dynamic-fault-p...
Spyros C. Kontogiannis, Grammati E. Pantziou, Paul...
ICMCS
2009
IEEE
102views Multimedia» more  ICMCS 2009»
14 years 7 months ago
Scalable HMM based inference engine in large vocabulary continuous speech recognition
Parallel scalability allows an application to efficiently utilize an increasing number of processing elements. In this paper we explore a design space for parallel scalability for...
Jike Chong, Kisun You, Youngmin Yi, Ekaterina Goni...
HPCA
2003
IEEE
15 years 10 months ago
Deterministic Clock Gating for Microprocessor Power Reduction
With the scaling of technology and the need for higher performance and more functionality, power dissipation is becoming a major bottleneck for microprocessor designs. Pipeline ba...
Hai Li, Swarup Bhunia, Yiran Chen, T. N. Vijaykuma...