544 search results - page 61 / 109 » Efficient checker processor design |
IPPS
2007
IEEE
15 years 4 months ago
2007
IEEE
Hardware accelerators are increasingly used to extend the computational capabilities of baseline scalar processors to meet the growing performance and power requirements of embedd...
ISCAS
2007
IEEE
15 years 4 months ago
2007
IEEE
— This paper presents performance and area evaluation of a homogeneous multiprocessor communication system based on network-on-chip (NoC) in FPGA platforms. Two homogenous chip m...
DATE
2006
IEEE
15 years 3 months ago
2006
IEEE
This paper presents the Block Processing Engine (BPE), an Application Specific Instruction-Set Processor (ASIP) explicitly designed for the implementation of multistandard wireles...
IPPS
2000
IEEE
15 years 2 months ago
2000
IEEE
This paper describes the design and implementation on MIMD parallel machines of P-AutoClass, a parallel version of the AutoClass system based upon the Bayesian method for determini...
JSA
2006
14 years 9 months ago
2006
This paper is devoted to scheduling a large collection of independent tasks onto heterogeneous clusters. The tasks depend upon (input) files which initially reside on a master pro...