555 search results - page 17 / 111 » Efficient event-driven simulation of parallel processor arch... |
95
Voted
IPPS
1994
IEEE
15 years 3 months ago
1994
IEEE
A parallel transputer-based emulator has been developed to evaluate the DDM--ahighlyparallel virtual shared memory architecture. The emulator provides performance results of a har...
CF
2007
ACM
15 years 3 months ago
2007
ACM
MppSoC is a SIMD architecture composed of a grid of processors and memories connected by a X-Net neighbourhood network and a general purpose global router. MppSoC is an evolution ...
102
Voted
ISCA
2006
IEEE
14 years 11 months ago
2006
IEEE
The assumption of maximum parallelism support for the successful realization of scalable quantum computers has led to homogeneous, "sea-of-qubits" architectures. The res...
107
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ICS
2007
Tsinghua U.
15 years 5 months ago
2007
Tsinghua U.
The register file is one of the most critical datapath components limiting the number of threads that can be supported on a Simultaneous Multithreading (SMT) processor. To allow t...
103
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ASPDAC
2004
ACM
15 years 3 months ago
2004
ACM
Abstract-- The power consumption of microprocessors has been increasing in step with the complexity of each progressive generation. In general purpose processors, this is primarily...