555 search results - page 19 / 111 » Efficient event-driven simulation of parallel processor arch... |
WSC
2001
14 years 11 months ago
2001
The problem of efficient load distribution and scaling of large-scale wireless communication system simulation on multiprocessor architectures (both shared memory and cluster arra...
PPOPP
2006
ACM
15 years 3 months ago
2006
ACM
IP forwarding is one of the main bottlenecks in Internet backbone routers, as it requires performing the longest-prefix match at 10Gbps speed or higher. IPv6 forwarding further ex...
INFOCOM
2007
IEEE
15 years 4 months ago
2007
IEEE
Next-generation high-end Network Processors (NP) must address demands from both diversified applications and ever-increasing traffic pressure. One major challenge is to design an e...
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DSD
2006
IEEE
15 years 1 months ago
2006
IEEE
Until now, most cryptography implementations on parallel architectures have focused on adapting the software to SIMD architectures initially meant for media applications. In this ...
MICRO
2007
IEEE
15 years 4 months ago
2007
IEEE
Modern chip multiprocessors (CMPs) are designed to exploit both instruction-level parallelism (ILP) within processors and thread-level parallelism (TLP) within and across processo...